As semiconductor devices have become highly integrated, the gate length of horizontal field effect transistors has become shorter and led to problems associated with short channel effects. Short channel effects can be associated with reduced electromigration and driving current due to increased impurity concentration in a channel layer of the horizontal field effect transistor. Junction leakage current can also be increased due to shallow junction depth of source/drain regions in the horizontal field effect transistor.
In an attempt to avoid such problems in highly integrated horizontal field effect transistors, fin type field effect transistors with three-dimensional structures have been developed.
A fin type field effect transistor can be formed on a silicon-on-isolator (SOI) substrate. The fin type field effect transistor on the SOI substrate can have a low junction capacitance, high scale ability, a high driving current, etc. However, when an upper silicon layer of the SOI substrate has a non-uniform thickness, the threshold voltage of the transistor can be readily changed. Further, the driving current can be deteriorated due to a self-heating effect. Such problems in a fin type field effect transistor may be avoided if the upper silicon layer is formed with at least a defined sufficient thickness and/or using circuit design technologies which have been exclusively used for SOI substrates.
However, the thickness of the upper silicon layer can limit feature size, or width, of a pattern in the fin type field effect transistor. Further, it can be very difficult to develop new circuit design technology, and the associated development cost may be unacceptably high.
When about 0V is applied to a gate electrode of the fin type field effect transistor, a channel region is fully depleted so that the short channel effect may not be generated. In contrast, it is difficult to obtain a threshold voltage of no less than about 0.1V due to the fully depleted gate electrode. However, to manufacture a desired integrated circuit, the threshold voltage is controllable in accordance with the desired integrated circuit. As a result, it can be necessary to configure the fin type field effect transistor with a threshold voltage of no less than about 0.1V.